Different types of flash memories may include NAND and NOR arrays which generally differ in the architecture of the memory array. Two types of popular NOR arrays are Serial Peripheral Interface (SPI) and parallel NOR arrays. The former (SPI) is characterized by the data being outputted from the memory in small segments (typically 1, 2 4 and/or 8 bits) while the latter (parallel) is characterized by the data being output to a user in larger segments (typically 8 or 16 bits). A user may be any apparatus or circuit configured to access the memory array and/or receive data from the memory such a processor, a buffer, an output and more.
NAND technologies may utilize error correction code (ECC) blocks to reduce errors in the outputted data from the array. Error correction for both SPI and parallel NOR proves more difficult since the data is output very quickly which in many products does not leave enough time for the calculations required for the ECC block. In order to save time and/or meet specification timing requirements parallel calculations may be utilized but at a substantial area increase/penalty/cost.
Several technologies may be utilized to produce NVM arrays such as floating gate, MirrorBit, additional charge trapping technologies and more.
Turning now to prior art FIG. 1, depicted is an NVM memory circuit 100 which includes am encoder 102 configured to encode data to be stored in/on Flash memory 104. Flash memory 104 may be a Non-Volatile flash Memory (NVM). Flash memory 104 may be read and data (r) may be output to decoder 106 which may include an ECC block. Based on the data (r) a Syndrome Generator 108 may relay the generated Syndrome(s) S to a Coefficient Calculator 110 which may further relay the coefficient(s) σto a Chien Search block/module/circuit 112. As depicted in element 114 which is a gate level example implementation of Chien search block 112, all n bits of data r are output and utilized in parallel to calculate the appropriate Chien search block 112 result for each appropriate bit ei. The resultant ei results are then transferred through a XOR gate 116 to inverse any incorrect bit and the resultant corrected data bits are output from the NVM memory circuit 100. The calculation of the Chien search block result ei is carried out substantially in parallel, the ei result for each data bit r is calculated in a dedicated circuit at substantially the same time, delays due to propagation and other electrical delays known in the art or otherwise may occur.